In recent years, the size reduction, weight reduction, and multifunctionalization of electronic equipment have proceeded considerably. With the size reduction of electronic equipment, the demand for further size reduction of package size becomes strong. As a product that addresses the size reduction of package size, the so-called Chip Size/Scale Package (CSP) having a size substantially equal to that of a semiconductor chip is proposed. This is a package having connection portions to an external wiring substrate in the mounting region rather than the peripheral portion of a semiconductor chip. Specific examples include one obtained by adhering a bump-attached polyimide film to a surface of a semiconductor chip, making electrical connections with the chip and gold leads, and then performing potting sealing with an epoxy resin (see the following Non Patent Literature 1), and one obtained by forming metal bumps on a temporary substrate at positions corresponding to connection portions to a semiconductor chip and an external wiring substrate, face-down-bonding the semiconductor chip, and then performing transfer molding on the temporary substrate (see the following Non Patent Literature 2).
On the other hand, regarding the formation of fine wiring, attention is paid to a semi-additive method in which a relatively thin plating layer is formed on a base material surface, a plating resist is formed thereon, a conductor is formed to a necessary thickness by electroplating, then the resist is peeled, and then the thin plating layer is removed by soft etching. In addition, a method of forming carrier-attached peelable copper foil formed by a heating-pressurization pressing method, instead of a thin plating layer, and then removing the carrier to form a thin copper foil layer is also studied.
In addition, for the purpose of providing a method for manufacturing a package substrate for mounting a semiconductor device having excellent wiring density and excellent production efficiency and high connection reliability, a method is proposed in which a supporting substrate for circuit formation obtained by providing an insulating resin on the carrier copper foil surface of carrier copper foil-attached ultrathin copper foil having an ultrathin copper foil thickness of 1 μm to 5 μm is used, a wiring conductor is fabricated on the supporting substrate for circuit formation using copper electroplating or the like, and then the carrier copper foil-attached supporting substrate is peeled to fabricate a package substrate for mounting a semiconductor device (for example, see the following Patent Literature 1).